NVIDIA “Vera” CPUs Contain PCIe Hardware Compatibility Flaw Impacting non-NVIDIA GPUs

NVIDIA recently released its “Vera” CPUs as standalone SoCs available to third parties, positioning them to compete with Intel’s Xeon and AMD’s EPYC processors. However, the “Vera” generation appears optimized specifically for NVIDIA GPUs, as the SoC contains a hardware bug that triggers errors when paired with non-NVIDIA graphics cards or accelerators. While CPUs traditionally function as general-purpose devices capable of connecting any third-party accelerator to the host platform, this does not appear to hold true for “Vera.” Specifically, AMD GPUs and other third-party accelerators may cause issues, as the “Vera” CPU generation suffers from a major hardware flaw that prevents reliable operation and system installation. The issue stems from how the PCIe controllers in “Vera” CPUs generate memory addresses.

Under certain conditions, they produce invalid addresses that disrupt reliable communication with third-party accelerators. This occurs during PCIe Memory-Mapped I/O (MMIO) write operations when the CPU attempts to write with partial byte enable to MMIO regions. The issue intensifies particularly when these regions are mapped using Arm’s Normal Non-Cacheable memory attribute “MT_NORMAL_NC,” creating significant compatibility problems. Because Arm employs more relaxed memory ordering for normal non-cacheable attributes, this can trigger the erratum, resulting in erroneous address generation, data corruption, and even PCIe device failure during DMA-intensive workloads…