NVIDIA has closed the option to remove hardware limits for tensor cores in the GeForce RTX 50 series.

NVIDIA uses the same GPU dies for its consumer and professional GPU lines, but artificially limits the performance of Tensor Cores when executing FP32 accumulation operations. On consumer models of the Turing, Ampere, and Ada Lovelace series, hardware fuses are blown during manufacturing, switching the processing of FP16, BF16, TF32, and FP8 input formats with FP32 accumulation to half-speed. On professional adapters, these same physical units operate at full speed. This limitation does not affect regular FP32 calculations on CUDA cores and does not directly impact frame rates in games, but it does significantly reduce performance in machine learning, image generation, and large language model inference tasks.

A buffer overflow vulnerability in the signed Booter microcode of the SEC2 security microcontroller allowed the restriction to be lifted on architectures up to and including Ada Lovelace. This bootloader is launched by the official Heavy Secure driver with the highest privilege level to initialize the GSP system processor. The exploit intercepts control while the microcode is running, overwrites the override register from HALF_SPEED to FULL_SPEED, and restarts the video…