Researchers from both Intel Corporation and Imperial College London collaborated on a technical paper titled “ROVER: RTL Optimization via Verified Electronic Graphics Rewriting.” The paper discusses the challenges in manual RTL design and optimization in the semiconductor industry, emphasizing the limitations of business logic and high-level synthesis tools compared to human designs. The researchers developed a tool called ROVER to automate the design space exploration by formulating datapath optimization as a graph rewriting problem. They created a set of mixed-precision RTL rewriting rules based on input from Intel designers and implemented an automated validation framework to ensure functional equivalence in design choices.
One of the key challenges in datapath design is determining the optimal order of transformations to apply, as it can vary depending on the specific design. ROVER addresses this challenge by utilizing the electron graph data structure to represent equivalent design implementations. By applying rewrites to this data structure, ROVER generates a set of efficient and functionally equivalent design choices. The researchers utilized ROVER on both Intel-provided and open-source benchmarks, observing up to a 63% reduction in circuit area. Additionally, ROVER can generate a custom library of distinct implementations from a parameterizable RTL design, improving circuit area across a range of instances.
To select an efficient implementation from the electron graph generated by ROVER, the researchers developed a theoretical cost metric and an integer linear programming model to extract the optimal implementation. To validate the generated designs, ROVER also produces a back-end verification certificate that can be verified with industrial tools, providing confidence in the optimized designs.
The technical paper, published in June 2024, provides a detailed insight into the methodology and results of using ROVER for RTL optimization. The researchers highlight the importance of automating design space exploration in RTL optimization to achieve significant improvements in circuit area efficiency. The Whitepaper can be accessed for further information on their findings and methodology.
In related reading, the researchers reference another technical paper titled “Combining Power and Arithmetic Optimization through Datapath Rewriting” by Intel Corporation and Imperial College London. This paper explores the merger of power and arithmetic optimization through rewriting data paths. Additionally, they discuss the challenges verification tools face in keeping up with the evolving verification flow and suggest that AI can play a significant role in improving these tools.
Overall, the collaboration between Intel Corporation and Imperial College London resulted in the development of ROVER, a tool that automates RTL optimization through verified electronic graphics rewriting. Their research demonstrates the significant impact of automating design space exploration in achieving efficient and functionally equivalent design choices in semiconductor datapath optimization.
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