Fault-tolerant quantum computing requires quantum error correction (QEC): Encoding one logical qubit into many physical qubits so that, below a threshold error rate, the logical error rate falls rapidly as the code grows. The practical engineering question is: How large must the code be and how good must the hardware be to reach a useful logical qubit? Credible answers require models that capture a device’s real error mechanisms, including coherent and correlated effects, yet run fast enough to support iterative design. These requirements motivate the design of hardware‑calibrated digital twins for QEC.
As a step toward this goal, we report on results from a collaboration involving researchers from Quantum Elements Inc., the University of Southern California (USC), Harvard University and Amazon Web Services (AWS), to speed up hardware-faithful QEC simulations with classical compute resources. Building on a real-time quantum Monte Carlo (QMC) algorithm developed…
