By Katie Tarasov
Publication Date: 2026-04-08 12:00:00
An underappreciated step in the chipmaking process is poised to become the next bottleneck for artificial intelligence.
Every microchip used to power artificial intelligence must be put into hardware that can interact with the outside world. But right now, almost all of this chipmaking step, known as advanced packaging, happens in Asia, and capacity is in short supply.
It’s now taking center stage as Taiwan Semiconductor Manufacturing Co. prepares to break ground on two new plants in Arizona and Elon Musk taps Intel for his ambitious custom chip plans.
“It can emerge as a bottleneck very quickly if people are not making the CapEx investments proactively to account for the surge in fab output that’s going to be coming in the next couple of years,” said John VerWey of Georgetown University’s Center for Security and Emerging Technology.
In a rare interview, TSMC North America packaging solutions head Paul Rousseau told CNBC that the numbers “are growing very substantially.”
Its most advanced method currently in use is called Chip on Wafer on Substrate, or CoWoS, and Rousseau said it is increasing at a stunning 80% compound annual growth rate.
AI giant Nvidia has reserved a majority of the most advanced capacity available at TSMC, which is the volume leader in packaging.
But Intel is technologically on par with the Taiwanese giant.
The U.S. chipmaker has struggled to solidify a major external customer for its chip fabrication business, but its packaging customers include Amazon and
