Intel, Samsung, and TSMC are leading the race to implement backside power delivery technology in their 2-nanometer nodes, aiming to enhance competitiveness in the AI chip market. This innovative technology relocates power supply networks to the back of silicon wafers, with Intel taking the lead in commercializing this year, followed by Samsung Electronics and TSMC gearing up for mass production in 2025. The industry is excited about the transformative impact of backside power delivery on chip efficiency, interference reduction, and overall performance.
Engineers face challenges in shrinking transistor sizes in semiconductor chips, posing obstacles to further miniaturization. The adoption of backside power delivery technology is expected to revolutionize semiconductor manufacturing and design, influencing future mobile application processors and AI chips positively.
Key points to note include:
– Intel’s leadership in deploying backside power delivery technology with PowerVia to enhance chip performance and efficiency.
– Competitive advantage: Backside power delivery technology improves energy efficiency and reduces interference, vital for AI applications and mobile processors.
– Industry shift: Samsung and TSMC are rapidly advancing their backside power delivery technologies, with Samsung aiming for mass production by 2025.
– Significant impact: The adoption of backside power delivery is expected to transform semiconductor manufacturing, enabling more compact and efficient chip designs, driving innovation across the industry.
The continuous pursuit of miniaturization in electronic technology has enabled the development of smaller, more powerful, and energy-efficient devices. However, the challenges of reducing transistor sizes are beginning to impede further miniaturization due to increased interference, lower energy efficiency, and limited space for circuits and power lines on the front side of chips.
Traditional methods of front-side power supply are inadequate for modern electronic devices, causing crosstalk, noise, and signal interference that degrade electronic component performance and increase energy consumption. Integration challenges due to front-side chip design limitations limit additional circuit and power line integration, restricting device capabilities as transistor density increases.
Intel’s backside power delivery technology, specifically PowerVia, is poised to revolutionize the semiconductor industry by improving chip performance, increasing energy efficiency, and reducing signal interference. Intel’s innovative approach in separating power distribution from signal routing enhances cell utilization efficiency to over 90%, crucial for high-performance AI and graphics applications requiring high-density chip designs.
The development of backside power delivery technology addresses interconnection bottlenecks and benefits mobile application processors requiring low power consumption and compact designs. Moreover, backside power delivery reduces the need for energy distribution layers, streamlining manufacturing steps and reducing semiconductor production costs.
Intel’s advancements with PowerVia exhibit performance improvements, including a 30% drop in platform voltage and a 6% increase in frequency performance. These enhancements are significant for overall AI chip performance, ensuring stable and efficient power supply critical for high-performance computing tasks.
By adopting backside power delivery, the semiconductor industry is paving the way for innovation in chip architecture and manufacturing processes, driving miniaturization and efficiency improvements in semiconductor technology. As leading chip manufacturers like Intel, Samsung, and TSMC progress in this field, the industry can anticipate compact and efficient designs, enhanced performance in AI applications, and new opportunities for innovation in chip architecture and manufacturing processes.
Article Source
https://www.electropages.com/blog/2024/07/intel-samsung-and-tsmc-race-towards-2nm-chip-technology
