Communication on Chip for Configurable Accelerators in Diverse SoCs (Columbia, IBM)

Communication on Chip for Configurable Accelerators in Diverse SoCs (Columbia, IBM)

Researchers from Columbia University and IBM’s Thomas J. Watson Research Center have released a technical paper titled “Toward Generalized On-Chip Communication for Programmable Accelerators on Heterogeneous Architectures.” The paper introduces a number of enhancements to the ESP platform to facilitate efficient on-chip communication for programmable accelerators on heterogeneous systems on chips (SoCs). These enhancements include … Read more