Researchers from Columbia University and IBM’s Thomas J. Watson Research Center have released a technical paper titled “Toward Generalized On-Chip Communication for Programmable Accelerators on Heterogeneous Architectures.” The paper introduces a number of enhancements to the ESP platform to facilitate efficient on-chip communication for programmable accelerators on heterogeneous systems on chips (SoCs). These enhancements include a flexible point-to-point communication mechanism between accelerators, a multicast Network on Chip (NoC) that can transmit data to multiple accelerators simultaneously, accelerator synchronization using the SoC coherence protocol, an accelerator interface providing fine-grained control over communication modes, and an ISA extension to support these improvements. The researchers have validated most of these features on FPGA prototypes and intend to incorporate them into the open-source version of ESP in the near future.
The authors of the paper are Joseph Zuckerman, John-David Wellman, Ajay Vanamali, Manish Shankar, Gabriele Tombesi, Karthik Swaminathan, Kevin Lee, Mohit Kapur, Robert Philhower, Pradip Bose, and Luca P. Carloni. The paper was published in July 2024 and can be found on arXiv under the title “Toward Generalized On-Chip Communication for Programmable Accelerators on Heterogeneous Architectures” with the reference number arXiv:2407.04182v1.
This research addresses the need for enhanced on-chip communication for programmable accelerators on heterogeneous architectures and proposes a set of solutions that can be implemented with minimal modifications to existing accelerators and SoC designs. The proposed enhancements aim to improve the flexibility and efficiency of communication between accelerators while adding negligible area overhead to the SoC architecture.
The paper outlines the contributions of this work, including the development of a point-to-point communication mechanism, a multicast NoC for simultaneous data forwarding, accelerator synchronization utilizing the SoC coherence protocol, a configurable accelerator interface for communication control, and an ISA extension to support these enhancements. The researchers have already tested most of these features on FPGA prototypes, demonstrating their feasibility and effectiveness in real-world scenarios.
Overall, this research presents a step forward in the optimization of on-chip communication for programmable accelerators on heterogeneous architectures, paving the way for more efficient and flexible designs in the future. By incorporating these enhancements into the open-source ESP platform, the researchers aim to make these advancements accessible to a wider community of developers and designers working on heterogeneous SoC architectures.
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https://semiengineering.com/on-chip-communication-for-programmable-accelerators-in-heterogeneous-socs-columbia-ibm/