By Tobias Mann
Publication Date: 2026-10-26 13:00:00
Like a virus, generative AI has invaded nearly every facet of technology, including chip and system design. If you ask Cadence Systems senior VP Paul Cunningham, somewhere between 20 and 30 percent of chips under development today are being designed with the help of AI agents, and that number is growing rapidly.
In many ways, Cadence’s latest products are among the clearest examples of how generative AI and HPC will coexist not just in industry but the sciences as well.
Over the past year or so, the EDA giant has rolled out a series of so-called “AI Super Agents,” including AuraStack for advanced packaging and PCB layout, ChipStack for SoC design and verification, InnoStack for PHY routing, and ViraStack for analog circuit design.
Much like Anthropic’s Claude Code or OpenAI’s Codex, these harnesses are designed to work with LLMs to automate design and testing flows by orchestrating Cadence’s existing EDA, test, and verification tools. This works for much the same reason that AI code assistants have exploded in popularity among software engineers. Code either compiles or it doesn’t. Similarly, Cadence has tests to verify and validate its designs will work as intended.
But just like many code assistants, the effectiveness of these tests depends heavily on how closely their training data resembles the inputs and outputs they’re fed. Cadence’s early agents were largely powered by off-the-shelf LLMs, which limited exposure to something like RTL.
“It’s not the…
