By TechPowerUp
Publication Date: 2026-08-14 09:56:00
Initially, NVIDIA will use SoIC 3D stacking technology to stack multiple chiplets into a single package, which will shorten the travel time between chips and reduce latency. These 3D chips will then be packaged side-by-side in a CoWoS-L or CoPoS packaging, creating a multi-kilowatt design capable of processing dozens of PetaFLOPS. For memory, NVIDIA will work with its partners to develop customized HBM, likely HBM4E, by the time “Feynman” reaches mass production. This customized memory includes a specialized base die that can contain logic elements like a memory controller or packet processing unit. Think of it as a way to pre-process data before it enters memory, or as a simple speedup, depending on what NVIDIA aims to achieve.
The final piece of the puzzle will be co-packaged optics (CPO), where NVIDIA will…



