Broadcom Helps CPU And XPU Makers Go Vertical With Compute

Given
the need to reduce the latency between components and to cram more and more
circuits into a socket for compute engines as well as network ASICs, it is
inevitable that chip designers will moved out of the two dimensional world and
start stacking up components.

We
have gone vertical with DRAM memory with HBM stacks, which is relatively simple
given the low power draw of memory chips compared to the ASICs that shuttle
data around and compute upon it. We have so-called 2.5D stacking that is used
on interposers to interconnect components like GPUs and XPUs to that HBM
stacked memory, and AMD pioneered 3D stacking of L3 cache chips with its Epyc CPUs.
Intel and AMD routinely use 3D stacking for cache memory on various CPUs and
GPUs now, and I have always wondered why this has not become the norm given
that it then allows for more compute cores to be put into a socket without
cutting back on the cache.

The
reasons we want to go vertical are intuitively obvious, just…